📌 Question

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000.

Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you’re not trying to do something more complicated).

What does “derive equations by inspection” mean?

One-hot state machine encoding guarantees that exactly one state bit is 1. This means that it is possible to determine whether the state machine is in a particular state by examining only one state bit, not all state bits. This leads to simple logic equations for the state transitions by examining the incoming edges for each state in the state transition diagram.

For example, in the above state machine, how can the state machine can reach state A? It must use one of the two incoming edges: “Currently in state A and in=0” or “Currently in state C and in = 0”. Due to the one-hot encoding, the logic equation to test for “currently in state A” is simply the state bit for state A. This leads to the final logic equation for the next state of state bit A: next_state[0] = state[0]&(~in) | state[2]&(~in). The one-hot encoding guarantees that at most one clause (product term) will be “active” at a time, so the clauses can just be ORed together.

When an exercise asks for state transition equations “by inspection”, use this particular method. The judge will test with non-one-hot inputs to ensure your logic equations follow this method, rather that doing something else (such as resetting the FSM) for illegal (non-one-hot) combinations of the state bits.

Although knowing this algorithm isn’t necessary for RTL-level design (the logic synthesizer handles this), it is illustrative of why one-hot FSMs often have simpler logic (at the expense of more state bit storage), and this topic frequently shows up on exams in digital logic courses.

💡 觀念解析與筆記

1. 什麼是「經由觀察推導公式 (By Inspection)」？

在 One-hot 編碼中，任何時刻有且僅有一個狀態位元為 1。這意味著我們不需要像二進位編碼 (Binary) 那樣大費周章地拿多個位元去經由邏輯閘解碼（例如 Binary 判斷狀態 C 需要 S1 & ~S0）。在 One-hot 中，要確認目前是否在狀態 C，直接拉 state[C] 這根導線來看它是不是 1 即可。

因此，推導次態公式時，只需要觀察狀態轉移表中「指向該狀態的所有輸入邊 (In-edges)」，並將這些可能直接用 OR (|) 結合起來：

  • 如何到達狀態 A？ 只有在「目前在 A 且 $in=0$」或「目前在 C 且 $in=0$」的時候。
  • 對應邏輯公式：assign next_state[A] = (state[A] & ~in) | (state[C] & ~in);

(注意：寫題時務必看對箭頭方向。若誤看成從該狀態出發的邊 (Out-edges)，邏輯就會完全錯誤。)

2. One-hot 的優點：真的比較簡單嗎？

單看一行公式可能會覺得用了許多 & 與 | 閘，但從「總體邏輯複雜度」來看，One-hot 大幅簡化了硬體結構：

  • 極省組合邏輯門 (Gate)：它把二進位編碼中原本需要在組合邏輯電路裡做的「解碼工作」，直接做在暫存器 (Flip-Flop) 的編碼上了。經過邏輯提取後，閘延遲 (Gate Delay) 極低。
  • 速度與時脈 (Clock) 的極致：因為少了解碼器的層層邏輯閘，訊號傳遞速度極快，能讓晶片運行的頻率飆得更高，非常適合內部觸發器豐富但組合邏輯較貴的 FPGA 架構。

3. 實務與現代 SoC 的考量

雖然 One-hot 在硬體速度上有絕對優勢，但在現代 SoC (晶片系統) 實務上並不會盲目使用，原因如下：

  • 面積與功耗的代價：一個 16 狀態的 FSM，Binary 只需要 4 個觸發器，One-hot 卻需要 16 個。在先進製程中，觸發器不論面積還是動態功耗都遠大於簡單的邏輯閘。
  • 狀態耦合與翻轉危機：萬一電路受到干擾（如宇宙射線、突波）導致 Single Event Upset (SEU)，使 One-hot 狀態從 0001 變成 0011（兩個狀態同時並存），會導致邏輯大亂、Bus 衝突甚至晶片鎖死。相較之下，二進位編碼能透過 default 機制安全地抓回錯亂。
  • 綜合工具的自動化：實務上設計師通常寫清晰易讀的 case 語法。綜合工具 (如 Design Compiler) 會根據 Timing 限制自動評估。除非速度真的卡死（如高速 Bus 仲裁器或跨時脈 FIFO 控制），否則現代 SoC 在一般控制型 FSM 上，反而更傾向使用 Binary 或 Gray Code。

🧑‍💻 Code Example

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A]&(~in)) | (state[C]&(~in));
    assign next_state[B] = (state[A]&(in)) | (state[B]&(in)) | (state[D]&(in));
    assign next_state[C] = (state[B]&(~in)) | (state[D]&(~in));
    assign next_state[D] = (state[C]&(in));

    // Output logic: 
    assign out = state[D];

endmodule

📚 Reference