Technique Learning Note

Welcome to my blog！
I will update my technical learning notes here. Recent Interests:

• Verilog
• IC Design
• Analog/Memory IC

📚 Recent Posts

• 📌 Conditional ternary operator
  Category: Verilog

• 📌 JTAG
  Category: Interfaces

• 📌 Dickson Charge Pump
  Category: Analog

• 📌 Avoid Latches
  Category: Verilog

• 📌 casez
  Category: Verilog

• 📌 4-to-2 Priority Encoder
  Category: Verilog

• 📌 Case Statement
  Category: Verilog

• 📌 Latch
  Category: Verilog

• 📌 Always if vs. Continuous assignment
  Category: Verilog

• 📌 Always Blocks
  Category: Verilog

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