Fsm1 (HDLBits)
Simple FSM 1 (asynchronous reset)
π Question
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1s, but using asynchronous reset.
β¨ Mealy State Machine v.s. Moore State Machine
In a Mealy state machine, the output depends on both the current state and the current input. In contrast, in a Moore state machine, the output depends only on the current state. This means that in a Moore machine, the output can only change on state transitions, while in a Mealy machine, the output can change immediately in response to input changes.
π§βπ» Code Example
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=1'b0, B=1'b1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A: next_state = (in) ? A : B;
B: next_state = (in) ? B : A;
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if (areset) begin
state <= B;
end else begin
state <= next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out = (state == B);
endmodule
π¬ Simulation Result