📌 Question

See Lfsr5 for explanations.

My solution of Lfsr5 is here: 5-bit LFSR (HDLBits)

Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.

🧑‍💻 Code Example

RTL Code

module top_module(
    input wire clk,
    input wire reset,    // Active-high synchronous reset to 32'h1
    output reg [31:0] q
); 

always @(posedge clk) begin
    if (reset)
        q <= 32'h1;
    else
        q <= {(q[0]^1'b0), q[31:23], (q[22]^q[0]), q[21:3], (q[0]^q[2]), (q[0]^q[1])};
end

endmodule

Testbench Code

`timescale 1ns/1ps

module tb_top_module;

    reg clk;
    reg reset;
    wire [31:0] q;

    top_module dut (
        .clk(clk),
        .reset(reset),
        .q(q)
    );

    initial begin
        reset = 0;
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        $dumpfile("tb_top_module.vcd");
        $dumpvars(0, tb_top_module);

        // Initialize
        # 10
        reset = 1;
        #10;
        reset = 0;

        // Observe shifting
        #100;

        // Reset again
        reset = 1;
        #10;
        reset = 0;
        
        // Shift
        #100;
        $finish;
    end
    
    initial begin
        $monitor("Time=%0t reset=%b q=%b", $time, reset, q);
    end

endmodule

🔬 Results

Simulation Waveform

Synthesis RTL-level Schematic

Synthesis Gate-level Schematic

📚 Reference